Non-volatile memory module

ABSTRACT

A non-volatile memory module includes a charging circuit, a battery couple to the charging circuit, a volatile memory and an electronic switch coupled between the volatile memory and the battery.

FIELD OF THE INVENTION

This invention relates to memory devices and more particularly memorymodules for use in disk storage sub-systems.

BACKGROUND OF THE INVENTION

As is known in the art, the increasing performance characteristics ofcentral processor units (CPUs) and memories has not generally beenmatched by similar performance increases in peripheral sub-systems. Thishas lead to the development of disk sub-systems which include diskmemory arrays implemented as redundant arrays of inexpensive disks(RAID).

As is also known, there are presently at least five differentorganizations of disk arrays which are generally referred to as RAIDlevels. For example, the so-called RAID level 5 or simply RAID-5 systemsrefer to those systems in which data and parity check information aredistributed across all disks in the disk array. Because of the dataintegrity and availability advantages provided by RAID-5 systems, thereis presently a trend to implement the RAID-5 data management protocol indisk storage sub-systems.

One problem with such disk storage sub-systems, however, is that thereexists a set of failure modes which can occur and which cannot beaddressed by the RAID-5 protocol or any other RAID protocol. Suchfailure modes may lead to corrupted and/or lost data. The corrupted orlost data may be restored by a user, however, such restoration mayinvolve considerable time and expense. It would, therefore, be desirableto increase the data integrity of disk storage sub-systems implementedas a RAID system, and in particular it would be desirable to increasethe data integrity of those disk storage sub-systems implementing aRAID-5 data management protocol.

There are several approaches to solving the problem of failure modesleading to corrupted and/or lost data in RAID systems. One approach tosolving this problem is to provide the disk sub-system with a memorymodule which includes an electrically erasable, programmable read-onlymemory (EEPROM). Data and parity check information may be stored in theEEPROM prior to being written onto the disk array. However, one problemwith this approach is that presently available EEPROMs can accommodateonly a limited number of write cycles before the EEPROM loses itsability to retain data. Presently, the number of guaranteed write cyclesof an EEPROM is in the order of 100,000 writes for relatively smalldevices and in the order of 10,000 writes in larger arrays. Furthermore,the array sizes are relatively small compared with other availablememory devices.

Another problem with the EEPROM approach is the relatively long writecycle time required. This is especially true when the write must beperformed on a byte by byte basis. However, even when a page write canbe employed, the write cycle time is typically in the range of tens ofmilliseconds for small page sizes.

Additionally, the cost per megabyte of memory for EEPROMs is relativelyhigh compared with other types of memories. Due to the above and otherlimitations, EEPROMS are thus typically used to hold data that changesinfrequently and not used for general system random access memory (RAM).

Another approach to solving the corrupted and/or lost data problem is toprovide a memory module having a flash memory disposed thereon. Theflash memory cell structure is similar to that of an EEPROM. Flashmemories, however, are provided in much smaller cell sizes than EEPROMs.Consequently, flash memories are provided having greater bit densitiesand thus are much more cost effective to manufacture (i.e. they have alower cost per megabyte than an EEPROM).

Flash memories, however, also have a limited number of write cycles.Typically, the number of write cycles is in the order of 10,000 cycles.Furthermore, flash memories have the added limitation that they cannotbe selectively erased. That is, the entire flash memory array must beerased and the time to erase a typical flash memory device is generallyabout one millisecond. Thus, flash memory devices are also typicallyused to hold data that changes infrequently.

It would thus be desirable to provide a non-volatile memory circuithaving a relatively low cost while still providing a reliable techniquefor improving the data integrity of a disk storage sub-system in whichthe non-volatile memory circuit is employed.

SUMMARY OF THE INVENTION

In accordance with the present invention, a non-volatile memory moduleincludes a battery, a charging circuit coupled to the battery, at leastone volatile random access memory (RAM) and a switch coupled between thebattery and the volatile RAM. With this particular arrangement, anon-volatile memory circuit for improving the data integrity of a diskstorage sub-system including a sub-system controller and a disk drive isprovided. The non-volatile memory circuit may be provided as anon-volatile single in-line memory module (NVSIMM) adapted to couple toa standard SIMM connector of a configuration well known in the art. TheNVSIMM may include a printed circuit board having the battery, chargingcircuit, volatile RAM and switch disposed thereon and having a connectordisposed on one edge thereof. The connector may be provided as a typemateable to a vertical or semi-vertical edge type connector disposed ona motherboard thus allowing the NVSIMM to be coupled to the motherboard.The volatile RAM may be part of a memory array having a desired memorysize based upon the packaging density given currently available memorydevices and the specific storage needs. The volatile RAM may beprovided, for example, as static random access memory (SRAM), apseudo-static random access memory (PSRAM) or a dynamic random accessmemory (DRAM). The particular type of volatile memory included in thememory array may be selected according to a variety of factors includingbut not limited to cost, reliability and availability. The battery maybe provided as one or more rechargeable lithium (Li) cells oralternatively, the battery may be provided as one or more nickel cadmium(NiCd) cells. The particular type and number of cells should be selectedto permit a relatively small module size while still being able toprovide sufficient power to the memory array such that the volatile RAMretains data for a predetermined time period.

The non-volatile memory module may be employed within a sub-systemcontroller. In the event a line voltage on the sub-system controllerdecreases below a predetermined threshold voltage, the switch couplesthe battery to the memory array thereby substituting the battery powerfor the normal power supply. Thus data and parity information remainstored in the volatile RAM of the memory array until the information canbe successfully written from the volatile RAM to the disk drive therebyavoiding any loss of information.

By providing the memory module as a single in-line memory module (SIMM),the memory module may be rapidly installed on or removed from thesub-system controller. If the sub-system controller fails, the NVSIMMcan be removed from the failed controller and installed on a replacementcontroller. Thus, the user can quickly resume system operation withoutloss of data.

This avoids the necessity of performing a so-called system reload, whichusually results in a loss of data and which is typically required aftera disk storage sub-system failure. The time required to perform a systemreload is generally between several hours and several days. Thus, thenon-volatile memory module minimizes the amount of system downtime inthe event of a sub-system controller failure.

The battery cells are charged by the charging circuit. The batterycapacity is selected in conjunction with the power requirements of thevolatile RAM such that the volatile RAM retains data for a predeterminedperiod of time, for example thirty days. A larger battery may, ofcourse, be used with a resultant greater data retention period. Byproviding the memory module as a SIMM, the memory module may be used asa drop in replacement for a conventional SIMM which does not include thedata retention characteristics of the present invention.

The memory module of the present invention, however, significantlyincreases the data integrity of the disk storage sub-system in the eventthe sub-system controller fails. Moreover, the present invention alsoprovides several additional advantages including an unlimited number ofread/write cycles, low power consumption, the use of low cost volatilememory, and high speed reads and writes.

In accordance with a further aspect of the present invention, anon-volatile single in-line memory module (NVSIMM) includes an array ofstatic random access memory (SRAM) integrated circuits disposed on aprinted circuit board fabricated in compliance with industry-standardspecifications for a single in-line memory module (SIMM). The NVSIMMfurther includes a battery circuit coupled to the SRAM array and acharging circuit coupled to the battery circuit. With this particulararrangement, an NVSIMM is capable of surviving spontaneous loss ofsystem power for an extended period of time without loss of data storedin the SRAM array. In one application, the NVSIMM may be provided as amemory module which is physically and electrically interchangeable witha volatile SIMM having a DRAM array disposed thereon. By providing thememory module with a conventional SIMM form factor and a connector, amodular, removable, high density memory array which is easily connectedto a supporting circuit board (motherboard) is provided. Thus the NVSIMMmay be replaced, reconfigured, upgraded and/or migrated to other diskstorage sub-systems.

The battery circuit includes a rechargeable battery and associatedcharging, voltage monitoring and supply switching circuitry. The batterycircuit is selectively coupled to the SRAM array via the switchingcircuitry. The battery provides a dedicated source of standby power forthe SRAM array. Thus, when system power is unavailable to the NVSIMM,the switching circuitry couples the battery circuit to the SRAM arrayand the SRAM array is able to maintain data integrity during powerinterruptions. The battery should be selected to have compatiblecharacteristics with the low standby current and the minimum retentionvoltage requirements of the SRAM array. The rechargeable battery may beprovided, for example, as a lithium battery having a high energydensity. The charging requirements, high cell voltage, wide thermaloperating range, and low self-discharge characteristic favor the use oflithium batteries on the NVSIMM module although other battery types maybe employed.

The NVSIMM further includes a voltage monitor circuit coupled betweenthe system power supply and the SRAM array. The voltage monitor circuitdetects power fluctuations and protects the SRAM array from spuriousaccess attempts during such power fluctuations. Thus since spuriousaccess attempts are precluded by the voltage monitor circuit, the SRAMarray provides a reliable technique for maintaining data integrity.Moreover, the back up process is self-initiated. That is, the memorymodule need not receive notification of impending power interruptionfrom the disk storage sub-system controller or any other external systemprior to initiating the back up power mode. Furthermore, the NVSIMM istotally passive; i.e. the NVSIMM does not require any clocks, statemachines, voltage translation circuitry or memory refresh circuitry.Thus, the NVSIMM backs up data in a highly reliable manner, withoutexternal controls.

The NVSIMM further includes a battery voltage monitoring circuit forproviding a signal indicative of battery state-of-charge. The NVSIMMalso includes a signal buffering circuit for reducing the incrementalloading presented by the NVSIMM to the motherboard on which it isinstalled. The NVSIMM thus increases data integrity and facilitatesservice of the host disk controller when included on such a controller.A plurality of NVSIMM modules may be configured as high speed storage ina non-volatile write-through write cache which is architecturallylocated in a data path between a host port and a back-end disk driveport on the sub-system controller. The write cache stores host-writtendata blocks and associated controller-generated parity blocks untilthese blocks are successfully written to the disk drive. The ability toretain host data in the write cache through power interruptions allowsthe sub-system controller to acknowledge a host write operation ascomplete at a much earlier point in the write translation, and inparticular, before the data is actually stored on the magnetic media.This increases the aggregate host write bandwidth. Since the NVSIMM isremovable and retains data in the SRAM array even during a power loss,write data stored on the NVSIMM can survive a loss of power on thesub-system controller. The NVSIMM modules can then be removed from thefailed sub-system controller and installed in a replacement controller.

As mentioned above, in one application the printed circuit board andSRAM memory array may be provided as mechanically and electricallyinterchangeable with existing volatile SIMM-based DRAM arrays of thetype commonly used in state of the art direct access storage device(DASD) controllers. Thus, the NVSIMM appears, to the DASD controller, tobe a conventional volatile SIMM having a DRAM array disposed thereon.

The NVSIMM provides a three-bit identification code to the sub-systemcontroller. The code identifies the module type, (e.g. NVSIMM), modulememory capacity and module battery status (e.g. battery voltage below apredetermined nominal voltage level). The NVSIMM operates as a volatileSRAM array if the battery is removed, shorted, discharged or dead. Afull battery charge may typically be accomplished in the range of about40 to 60 hours. Useful battery capacity, however, is restored typicallyin under ten hours. In one embodiment, the battery charger circuit maybe provided as a constant voltage circuit which charges the battery, ifnecessary, whenever system power is present.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing features of this invention as well as the invention itselfmay be more fully understood from the following detailed description ofthe drawings in which:

FIG. 1 is a block diagram of a disk storage sub-system including amemory array having a non-volatile memory circuit;

FIG. 2.is a block diagram of a non-volatile memory circuit;

FIG. 3 is a schematic diagram of a non-volatile memory circuit;

FIG. 3A. is a schematic diagram of a battery voltage monitoring circuit;

FIG. 4 is a top view of a non-volatile single in-line memory module;

FIG. 4A is a bottom view of the non-volatile single in-line memorymodule shown in FIG. 4; and

FIG. 5A-5B are schematic diagram of a battery charging and controlcircuit.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now to FIG. 1, a disk storage sub-system 10 which includes asub-system controller 12, for controlling the timing and data managementon storage sub-system 10. Sub-system controller 12 may include, forexample, a microprocessor and associated memory and interrupt generatorcircuits.

A host interface circuit 18 has a first port 18a coupled to sub-systemcontroller 12, a second port 18b for coupling to a host processor (notshown) and a third port 18c coupled to a control logic circuit 20 at afirst control logic port 20a. Address, data and control signals areprovided to port 18a while ports 18b, 18c accommodate signals related todata movement of read/write data. Port 18b may be provided, for example,as a SCSI or IPI or any other type of interface adapted to handlecontrol, data and/or address information. Port 18c is adapted to handlesignals having control and/or data components.

A second port 20b of control logic circuit 20 is coupled to sub-systemcontroller 12 via a bus 22 and a third port 20c of control logic circuit20 is coupled via a bus 24 to a drive interface circuit 26 at a firstport 26a. A second port 26b of drive interface circuit 26 is coupled tosub-system controller 12 and a third port 26c of drive interface circuit26 is coupled through a system bus 27 to a disk drive 28. Disk drive 28is here shown to include a redundant array of inexpensive disks 28a-28N.Thus in this particular embodiment sub-system 10 corresponds to a RAIDdisk storage sub-system. The NVSIMM is particularly suitable for use ina write cache of a disk system.

A memory array 30 is coupled to control logic circuit 20 via a bus 31.Memory array 30 includes a plurality of non-volatile memory modules32a-32N generally denoted 32 and an optional dynamic random accessmemory module (DRAM) 34. As will be described in more detail below inconjunction with FIGS. 2-5B, each of the non-volatile memory modules 32includes at least one volatile memory device. The control logic circuit20 receives data and address signals from sub-system controller 12 andin response thereto directs the movement of data between particularaddress locations in memory array 30 and host and drive interfacecircuits 18 and 26.

Memory array 30 is provided as a write-through write cache memorydisposed between host interface 18 and disk drive interface 26.Non-volatile memory modules 32 thus store host-written data blocks andassociated parity blocks generated by sub-system controller 12. Thenon-volatile memory modules 32 store the data and parity information inthe volatile memory devices until these blocks are written to disk drive28. When the data and parity information are written across all of thedisk drives 28a-28N in a so-called striping technique, disk-storagesub-system 10 is operating as a RAID-5 disk storage sub-system.

As will also be described in detail below in conjunction with FIGS.2-5B, non-volatile memory modules 32 receive system power via sub-systemcontroller 12. Memory modules 32 also includes a stand alone powersource independent of sub-system controller 12. Thus, memory modules 32are able to retain host data in the volatile memory devices even ifpower is not supplied thereto by sub-system controller 12.

The ability to retain host data in memory modules 32 allows sub-systemcontroller 12 to acknowledge host write operations as complete beforethe data is actually stored on disk drive 28. Since memory modules 32retain data therein if power to sub-system controller 12 is lost or ifsub-system controller 12 fails, memory modules 32 can be physicallyremoved from the failed sub-system controller and re-installed in areplacement sub-system controller. Thus in the event of system powerloss or failure of sub-system controller 12, memory modules 32 preservethe data integrity of the disk-storage sub-system 10.

Referring now to FIG. 2, a non-volatile memory circuit 35 which may beof the type used in sub-system 10 described above in conjunction withFIG. 1, includes an address buffer 36 having a first port 36a coupled toa plurality of address lines generally denoted 38. A second port 36b ofaddress buffer 36 is coupled to a volatile memory array 40 at a firstport 40a. Address buffer 36 may accept any desired number of addresslines. In the present example 20 address lines are employed. Volatilememory array 40 may be provided for example as an array of static randomaccess memories (SRAMs), an array of a pseudo-static random accessmemories (PSRAMs) or as an array of dynamic random access memories(DRAM). In some applications, it may be desirable for memory array 40 toinclude more than one of the memory types mentioned above.

A plurality of data lines 42 are coupled to a data buffer 44 at a firstport 44a. A second port 44b of data buffer 44 is coupled to an inputport 40b of volatile memory array 40.

A plurality of control lines 46 are coupled to a control buffer 48 at afirst port 48a. A second port 48b of control buffer 48 is coupled alonga signal path 50 to a third port 40c of volatile memory array 40. Signalpath 50 is also coupled to a control circuit 52.

A system voltage V_(SIMM).sbsb.--_(VCC) is also coupled to the controlcircuit 52 via a signal path 53. Control circuit 52 includes a voltagedetection circuit which determines whether the system voltageV_(SIMM).sbsb.--_(VCC) is above or below a predetermined threshold.Control circuit 52 also includes switching circuits to perform switchingfunctions. The switching circuits of control circuit 52 receive controlsignals from the detection circuit. The control signals take on valuesindicative of the voltage level of the system voltageV_(SIMM).sbsb.--_(VCC). When the system voltage V_(SIMM).sbsb.--_(VCC)falls below a predetermined threshold voltage, the switching circuits ofcontrol circuit 52 decouple the volatile memory array 40 from the systemvoltage V_(SIMM).sbsb.--_(VCC) and couple the battery 59 to the volatilememory array 40 to thus provide battery voltage to the memory array 40.

Thus, the control circuit 52 includes switching circuitry to couple oneof a plurality of voltage sources to the volatile memory array. Controlcircuit 52 also includes switching circuitry to switch a supply voltageto the SIMM card, to thus control voltage provided to the SIMM moduleitself. The control circuit 52 further includes switching circuitry tocharge the battery, when instructed to do by the charging circuit 56.

It should also be noted that when memory array 40 is provided as aPSRAM, sub-system controller 12 (FIG.1) implements a refresh cycle inthe PSRAM to save data stored therein. To place the PSRAM in a refreshcycle mode sub-system controller 12 sends a signal to control circuit52. Thus, the PSRAM may be placed in either a standby mode or a refreshcycle mode via sub-system controller 12 and control circuit 52.

Control circuit 52 is coupled via signal path 54 to a charging circuit56 and charging circuit 56 is coupled via signal path 57 to the batterycircuit 58. Charging circuit 56 monitors the voltage level of thebattery 59 and provides charge control signals to control circuit 52 toensure that battery 59 is able to provide sufficient voltage to memoryarray 40 such that memory array 40 is able to reliably retaininformation stored therein when memory array 40 is powered by thebattery 59.

As will be described further below in conjunction with FIGS. 3-5B,battery circuit 58 includes a battery 59 and switch circuitry. Battery59 may be coupled to memory array 40 via the switch circuitry of batterycircuit 58. Battery 59 provides a battery voltage to memory array 40when memory array 40 is coupled thereto. Battery 59 is coupled to memoryarray 40, for example, when the system voltage V_(SIMM).sbsb.--_(VCC) isbelow an established threshold.

An optional temperature monitor circuit 60 is coupled to chargingcircuit 56. Temperature monitor circuit 60 should preferably be usedwhen battery circuit 58 includes Nickel-Cadmium (NiCd) battery cells.NiCd batteries should not be charged outside a particular temperaturerange. Thus, temperature monitor circuit 60 prevents charging circuit 56from providing a charging current signal to battery circuit 58 outside apredetermined temperature range.

It should be noted that if the operating temperature range of battery 59is within the operating temperature range of memory circuit 35,temperature monitor circuit 60 may be omitted from memory circuit 35.

If temperature monitor circuit 60 is included in circuit 35, chargingcircuit 56 receives both a temperature sense signal from the temperaturemonitor circuit 60 and a voltage level sense signal from control circuit52. Thus, control circuit 52 provides signals to charging circuit 56 andalso receives signals from charging circuit 56 to either allow chargingor not allow charging based on the level of the V_(SIMM).sbsb.--_(VCC)voltage and the battery temperature.

In a first embodiment, referring to FIG. 3, a non-volatile memorycircuit 62 includes a connector 64 through which are fed a plurality ofdata lines 66a-66M generally denoted 66, a plurality of address lines68a-68N generally denoted 68, a plurality of control lines 70a-70d,generally denoted 70, a system voltage supply line 72 and a SEAL signalline 74. Data lines 66 are coupled through connector 64 to a first port76a of a buffer circuit 76. Buffer circuit 76 includes a plurality ofdata buffers 78a-78Q. Data buffers 78a-78Q are coupled at data bufferport 76b to a volatile memory array (not shown). A data bus is coupledbetween data buffer port 76b and a memory array which may be similar tomemory array 40 (FIG. 2) to carry data to or from memory array 40.

Similarly, address lines 68 are coupled through connector 64 to acorresponding plurality of input ports 80a-80N of an address multiplexer81. A like plurality of output ports 82a-82N of address multiplexer 81are coupled via a bus 84 to corresponding address lines of the volatilememory array.

Address signals are provided from sub-system controller 12 (FIG. 1) toinput ports 68a-68N of connector 64. The addresses may be provided as atime multiplexed address. Thus, the first ten address bits are deliveredto multiplexer input ports 80a-80N and a predetermined period of timelater the second ten address bits are delivered.

The first ten address bits typically correspond to the row address andare latched into address multiplexer 81 by a row address strobe signal(RAS) fed into circuit 62 on input port 70a. The second ten bitstypically corresponding to the column address are latched into addressmultiplexer 81 by a column address strobe signal (CAS) fed into circuit62 on input port 70c. In this particular embodiment, the second ten bitsare latched into address multiplexer 81 via the row address strobedelayed signal (RASD) fed into circuit 62 on port 70b. The time betweenlatching the first and second ten bits in multiplexer 81 is based uponthe access time of the memory as well as set up and pulse widthrequirements which determine the minimum delay time between addressassertions, etc.

For example, in some applications it may be advantageous fornon-volatile memory circuit 62 to emulate or mimic a DRAM SIMM. A DRAMtypically has an access time of about 60-70 nanoseconds (nsec) and alsohas a set up time to accommodate pulse width requirements. In thisexample sub-system controller 12 provides timing signals compatible witha DRAM. Consequently, the row and column information is received basedon the timing requirements of a DRAM. Thus, memory circuit 62 wouldaccept the timing signals for a dram provided by sub-system controller12 even though memory circuit 62 may not include any DRAMs.

In an alternate embodiment, sub-system controller 12 may provide timingsignals compatible with an SRAM. In this case all twenty address bitsmay be provided to the SRAM in parallel rather than in first and secondten bit segments.

Address bus 84 is also coupled to an input port 86a of a control circuit86 such that the high order three bits of the address on bus 84 arecoupled into control circuit 86. Control circuit 86 includes a three toeight line decoder circuit 87. Decoder circuit 87 decodes the threeaddress bits fed thereto into one of eight unique output signals andprovides a corresponding signal on one of a plurality of chip enablesignal ports CE0-CE7. Thus, the high order three bits coupled fromaddress bus 84 define which memory bank of a plurality of memory banksis being addressed at any given time. Although here decoder circuit 87can enable at most eight memory banks, those of ordinary skill in theart will recognize that the memory array could include fewer or morethan eight memory banks. If the memory array includes more than eightmemory banks a larger number of bits for the purpose of bank selectionmust be provided. Thus, in this event, decoder circuit 87 may beprovided for example as a four to sixteen line decoder, assuming ofcourse that the memory array has no more than sixteen memory banks.

Each of the output lines of decoder 87 are coupled to one of a pluralityof control circuit output ports through a corresponding one of aplurality of series resistors 88 as shown. Series resistors 88 aid indecreasing the rate of change of the signal to thus improve signalquality by, for example, reducing the amount of undershoot and overshootof the signals.

Each of the output signal lines of decoder circuit 87 is coupled to apull up resistor in a resistor bank 89. Pull up resistors 89 have afirst terminal coupled to a nonvolatile voltage V_(NV).sbsb.--_(VCCA)provided by a battery 59 (FIG. 2) rather than to a system voltage V_(cc)provided by a system voltage supply via input port 72. Consequently,when circuit 62 operates in a back up mode and system voltage V_(CC) isnot available, resistors 89 are coupled to a back up power source whichprovides non-volatile voltage V_(NV).sbsb.--_(VCCA) and assures that thechip enable signals CE0-CE7 are pulled high during back up mode to thusreduce the current requirements of the SRAM array.

As mentioned above, control lines 70a-70d couple the RAS, RASD, CAS andwrite-enable WE signals to a corresponding plurality of input ports90a-90d of a control circuit 90. Control circuit 90 includes aninverting buffer circuit 92 and a plurality of logic circuits 94-108.Logic circuits 94-108 are provided as either NAND gates or NOR gates.Those of ordinary skill in the art will recognize of course that thefunction of control circuit 90 can be achieved using any type ofappropriate logic circuitry. Control circuit 90 provides at output port90a a row latch signal RLAT which corresponds to the logical OR of theRAS and the RASD signals.

The RLAT signal latches the column address in address multiplexer 81 andholds it unchanged for the duration of the access cycle. Thus, thecolumn address component of address multiplexer 81 is transparent untilthe RLAT signal asserts at which time the multiplexer contents are heldunchanged and are unaffected by signals on input ports 80a-80N.

The contents of multiplexer 81 remain stable to thus provide the SRAMarray a stable address until the cycle is terminated and the RASD signalgoes away at which time multiplexer 81 again accepts address inputsignals at input ports 80a-80N.

A pair of output enable signals OE₋₋ A and OE₋₋ B provided at logiccircuit output ports 90b, 90c enable memory array driver circuits. Thus,during a read cycle when data is being read from the memory array,signals OE₋₋ A and OE₋₋ B activate the SRAM driver circuits.

The output enable signals OE₋₋ A and OE₋₋ B are functionally identical,however, two signals are used for reasons of drive capability. That is,it is undesirable to couple an excessive number of inputs to a singlesignal, thus two signals are here used. Thus one-half of the memoryarray is coupled to a first one of the output enable signals (e.g. OE₋₋A) and the other half of the memory array is coupled to a second one ofthe output enable signals (e.g. OE₋₋ B).

A pair of write enable signals WE₋₋ A and WE₋₋ B are provided at logiccircuit output ports 90d, 90e. In a manner similar to output enablesignals OE₋₋ A, OE₋₋ B, write enable signals WE₋₋ A, WE₋₋ B each driveone-half of the memory array.

Output enable signals OE₋₋ A, OE₋₋ B are asserted only during a readcycle and conversely write enable signals WE₋₋ A, WE₋₋ B are assertedonly during a write cycle. Buffer circuit 92 receives a signal on one ofa plurality of input ports 92a-92h and provides an inverted signal on acorresponding one of a plurality of output ports 93a-93h.

Logic circuits 96, 98 are provided as NAND gates and receive at firstinput ports 96a, 98a the RAS signal from output port 93b of inverter 92.NAND gate 96 receives at a second input port 96b the CAS signal. NANDgate 98 receives at a second input port 98b the write enable signal WE.The RAS signal indicates that an access cycle is presently occurring andthat a subsequent CAS or WE signal should be used in this cycle. Thusthe presence of the RAS signal indicates that the CAS or write enable WEsignal is valid.

In the presently disclosed embodiment, the CAS signal is de-assertedonly during read cycles and the write enable signal WE is de-assertedonly during write cycles. Thus the signals provided by logic gates 96,98 are mutually exclusive signals and thus output enable signals OE₋₋ A,OE₋₋ B and write enable signals WE₋₋ A and WE₋₋ B are mutually exclusivepairs of signals.

The signals coupled between control circuit output ports 90f, 90g anddata buffer ports 76c, 76d are used to control the data transceiversthat either receive data from sub-system controller 12 or deliver datato sub-system controller 12 depending on whether a read or write cycleis being executed.

Buffer circuit 76 has a pair of ports 76c, 76d. Port 76c corresponds toa direction port DIR which alerts data buffer 76 the direction in whichdata is flowing. Port 76d corresponds to an enable port EN whichdetermines when to actually turn on the driver circuit in the selecteddirection.

Logic circuits 100-108 provide a direction signal DIR and an enablesignal EN to control ports 76c, 76d of data buffer 76. The direction andenable signals DIR, EN are provided in the following manner. Logiccircuit 100 is provided as a NAND gate and receives the RAS signal on afirst input port thereof. A second input port of NAND gate 100 iscoupled to an output port of logic circuit 102 which is provided as aNOR gate

NOR gate 102 has a first input port coupled to the output port of NANDgate 100. A second input port of NOR gate 102 is coupled to the outputport of NAND gate 98. Thus, when the RAS and WE signals are present atthe input ports of NAND gate 98, NOR gate 102 receives a write signal WRat the second input port.

The output port of NOR gate 102 is coupled to a first input port of aNAND gate 104. A second input port of NAND gate 104 is coupled toground. Thus NAND gate 104 provides a logic one signal to first inputports of NOR gates 106, 108. The output of NOR gate 108 is coupled toinput port 76d of buffer circuit 76. Thus NOR gate 108 sources theenable signal EN to buffer circuit 76.

The output of NOR gate 106 is coupled to input port 92h of invertercircuit 92. Output port 93h of inverter 92 is coupled to input port 76cof buffer circuit 76. Thus, logic circuits 96-108 decode the directionsignal and inverter 92 provides a direction signal DIR to input port 76cof data buffer 76.

Thus logic circuit 90 decodes the control signals RAS, RASD, CAS and WEprovided by sub-system controller 12 (FIG. 1) and provides direction andenable signals DIR, EN to data buffer 76.

Logic circuit 90 also extends the enable signal EN such that the outputenable signal EN is asserted for the full cycle. This is accomplished byNAND gate 100 and NOR gate 102 performing a sample and hold function onthe enable signal EN. During a write cycle when NAND gate 98 initiallyprovides a signal having a logic level one to the input port of NOR gate102 the output enable EN signal is activated. A predetermined period oftime later the write enable signal WE is no longer present at the inputport of NAND gate 98.

However, even after the write enable signal WE is no longer present,NAND gate 100 continues to provide a signal to the second input port ofNOR gate 102. This causes the output enable signal EN to be provided todata buffer port 76d until the RAS signal is removed from the firstinput port of NAND gate 100. Thus, the enable signal EN cannot beasserted until the write enable signal WE is provided, however, when thewrite enable signal WE is de-asserted the output enable signal ENremains present until the RAS signal is removed.

Thus, logic circuits 100, 102 perform both a decoding function and atiming function by stretching the cycle of the output enable signal ENbeyond the cycle of the write enable signal WE. This techniqueguarantees that data from the memory array is not removed beforesub-system controller 12 instructs the memory array to write the data.

Supply voltage V_(CC) is coupled from input port 72 to an input port110a of a voltage monitor circuit 110. Voltage monitor circuit 110monitors the level of system supply voltage V_(CC). If the voltage levelof supply voltage V_(CC) falls below a predetermined threshold level,voltage monitor 110 provides at an output port 110b an output signalPFAIL. Signal PFAIL is coupled to an input port 86b of decoder 86. Whendecoder circuit 86 receives signal PFAIL at terminal 86b, decoder 86de-asserts each chip enable signal CE0-CE7 and thus prevents any accessto the memory array.

Supply voltage V_(CC) is also coupled to a battery circuit 112 at afirst input port 112a. Supply voltage V_(CC) is coupled through a pairof series resistors 114, 116 to a node 118. A first diode 120 has ananode coupled to node 118 and a cathode coupled to a positive terminalof a battery 122. A second diode 124 here provided as a zener diode hasa cathode coupled to node 118 and an anode coupled to a negativeterminal of battery 122 and to ground. Resistors 114, 116 and diodes120, 124 form a battery charging circuit which provides a charge currentto battery 122.

Battery circuit 112 is coupled through a resistor 126 to a batteryswitching circuit 130. Resistor 128 is provided as a pull down resistorfor the SEAL signal. Battery switching circuit 130 here includes a pairof switching circuits 132, 134. Switching circuits 132, 134 may beprovided, for example, as the type manufactured by Maxim corporation andidentified as part number MAX1259. Those of ordinary skill in the artwill recognized of course that any equivalent electronic switchingdevice may also be used.

Resistor 126 has a first terminal coupled to the positive terminal ofbattery 122 and a second terminal coupled to an input port of batteryswitching circuit 130. Resistor 126 is disposed such that if any circuitcomponent fails (e.g. short circuits) resistor 126 limits the amount ofcurrent which may be provided to battery 122. Thus, if switching circuit132 or 134 fails and provides a low impedance path between the terminals132a, 132b or 134a, 134b, battery 122 will not be directly connected tothe supply voltage V_(CC). Rather resistor 126 acts as a currentlimiting resistor in series between the supply voltage V_(CC) and thepositive terminal of battery 122. Resistor 126 thus provides a measureof a safety to avoid an explosion of battery 122 caused by switchingcircuit 132, 134 failure.

Battery switching circuit 130 has a pair of output ports 130a, 130bwhich are coupled to a non-volatile memory array (not shown). As will beexplained in detail in conjunction with FIGS. 4 and 4A below, eachswitching circuit 132, 134 is coupled to one-half of memory devices inthe non-volatile memory array.

Switches 132, 134 are coupled such that they each receive the samebattery input signals and the same supply voltage signal V_(CC) at therespective input ports 132a, 132b, 134a, 134b thereof. Switches 132 and134 are each coupled to input port 72 and monitor supply voltage V_(CC).When switch circuits 132, 134 sense a drop in supply voltage V_(CC),switches 132, 134 couple battery 122 to the memory array and thusprovide a non-volatile voltage V_(NC).sbsb.--_(VCCA),V_(NV).sbsb.--_(VCCB) at output ports 130a, 130b respectively.

Switch 134 also has a second function. When supply voltage signal V_(CC)falls below a predetermined threshold voltage, switch 134 provides apower fail output signal PF to logic circuit 136.

In this particular embodiment, the predetermined threshold voltagecorresponds to a voltage typically of about 1.26 times the batteryvoltage. The battery voltage here corresponds to about 3.0 volts andthus the threshold voltage corresponds to approximately 3.75 volts. Thuswhen the system voltage V_(CC) falls below 3.75 volts, switching circuit134 asserts a power fail signal PF on signal line 130c. Output port 130cis coupled to an input port of a logic circuit 136.

When the system voltage continues to decay to the level of the batteryvoltage, V_(CC) is disconnected from the memory array and the batterycircuit 112 provides the source of power to the array through theswitches 132, 134. Thus, it should be noted that no externalintervention is necessary to cause memory circuit 62 to initiate thepower back up mode; the application of back up power being initiated andapplied within the memory circuit 62.

A control signal SEAL is coupled to an input port 130d of batteryswitching circuit 130. When the SEAL signal is applied, the next timesupply voltage V_(CC) is removed, battery 122 will not back up the SRAMarray. That is, the back up function provided by battery 122 can beprogrammably disabled via switch circuit 130 to thus prevent batterydischarge before non-volatile memory circuit 62 is placed in an activesystem. Thus battery 122 is sealed for storage by the SEAL signal.

When the SEAL signal is first asserted, no effect is immediatelyapparent. However, the affect becomes apparent when supply voltageV_(CC) is removed and data is not retained in the memory array due toloss of power. Thus, the SEAL signal may be advantageously asserted, forexample, after non-volatile memory circuit 62 is tested but before it isshipped to a customer to prevent battery 122 from discharging prior tofinal installation.

Backup mode is automatically re-enabled upon subsequent restoration ofsystem voltage V_(CC). Thus, in a manufacturing environment, the batteryon each NVSIMM should be fully charged and the backup function disabledprior to shipment. The minimum shelf life of an unpowered non-volatilememory circuit 62 having the back up function disabled, and thus adisconnected battery, is dependent upon the particular type of batteryused and is typically about ten years for a lithium battery.

Many of the circuit components disposed on the motherboard to whichmemory circuit 62 may be coupled operate reliably only when thecomponents receive at least 4.5 volts. Thus, these circuit componentsfail to operate predictably whenever the voltage provided thereto dropsbelow 4.5 volts. It is desirable to therefore protect the SRAM arrayfrom spurious access attempts which may occur at a voltage leveltypically at or below approximately 4.5 volts.

Therefore, voltage detection monitor circuit 110 detects if supplyvoltage V_(CC) falls below a second predetermined threshold ofapproximately 4.5 volts. If supply voltage V_(CC) falls below 4.5 volts,voltage detection circuit 110 provides a PFAIL signal which prevents allaccess to the volatile memory array.

Voltage detection circuit 110, however, fails to operate below a thirdpredetermined threshold voltage corresponding to approximately 1 volt.Since supply voltage V_(CC) will eventually reach zero volts it isnecessary to maintain the SRAM protection function. Thus batterymanagement circuit 134 provides signal PF when V_(CC) falls below 3.75volts.

Thus, voltage detection circuit 110 initially detects the supply voltageV_(CC) falling below 4.5 volts. Voltage detection circuit 110 thenasserts signal PFAIL which is fed to logic circuit 136 to de-assert thefour chip enable output signals CE_(A) -CE_(D).

Logic gates 136a-136d are provided as logic AND gates. Thus chip enablesignals CE_(A) -CE_(D) are asserted when both the PFAIL signal providedby voltage monitor circuit 110 and the PF signal provided by batterymanagement circuit 134 are fed to logic circuit 136. The volatile memoryarray is thus protected from spurious access attempts which may occurdue to the decreasing system supply voltage V_(CC).

It should be noted that each of the logic gates 136a-136d are powered bythe non-volatile voltage signal V_(NV).sbsb.--_(VCCB) provided atbattery switching circuit output port 130b during back up mode. Thus,logic circuit 136 remains powered and active during back up mode.

The supply voltage V_(CC) is constantly being monitored by monitorcircuit 110 and battery switching circuit 130. When the supply voltageV_(CC) initially decreases, voltage detection circuit 110 firstinitiates the memory array protection function by providing signalPFAIL. As supply voltage V_(CC) continues to decrease, battery switchingcircuit 130 via switch 134 maintains the protection function byasserting the PF signal.

It should be noted that although logic circuit 136 is here coupled toswitch 134, logic circuit 136 could alternatively be coupled to switch132. The additional loading on switch 132 or 134 due to logic circuit136 should be selected to have a minimal loading effect on switchcircuit 130. That is, the loading effect on switch circuit 130 due tologic circuit 136 should preferably be a small percentage of the overallload on switch 130.

It should be noted that in order to guarantee that the SRAMs meet theirmaximum back-up current requirement specifications, all chip enablesignals presented to back up memory array should be de-asserted towithin 0.2 volts of their respective rail voltage. If the memory arrayis provided as an array of SRAMs, previously written data may beretained reliably when the SRAMs are powered by as little as two volts.

Those of ordinary skill in the art will recognize that as technologyimproves it may be possible that volatile memory devices may retainpreviously written data with voltages less than two volts.

Referring now to FIG. 3A, a battery voltage monitoring circuit 150 has abattery voltage terminal 150a, a supply voltage terminal 150b, areference voltage terminal 150c and an output port 150d. A batteryvoltage V_(BATT) is coupled through battery voltage terminal 150a to aninput port of a comparator 151. A supply voltage V_(CC) is coupledthrough supply voltage terminal 150b to a first port 152a of a referencevoltage circuit 152. A second port 152b of reference voltage circuit 152is coupled to a second input port of comparator 151.

Reference voltage circuit 152 includes a first resistor 153 having afirst terminal coupled to supply voltage terminal 150b and a secondterminal coupled to a cathode of a zener diode 154 at a node 155. Ananode of diode 154 is coupled to a first reference potentialcorresponding to ground.

A second resistor 156 has a first terminal coupled to node 155 and asecond terminal coupled to the second input port of comparator 151. Athird resistor 157 and a capacitor 158 are coupled between the secondterminal of resistor 156 and ground. An output port of comparator 151 iscoupled to output port 150d of battery voltage monitoring circuit 150.

Diode 154 establishes through resistor 156, a reference voltage V_(REF),at the second input terminal of comparator 151. When the battery voltageV_(BATT) has fallen below the reference voltage V_(REF) comparator 151provides an output signal at port 150d.

The output of battery voltage monitoring circuit 150 is fed tosub-system controller 12 (FIG. 1). This may be accomplished, forexample, by coupling port 150d through connector 64 (FIG. 3) tosub-system controller 12. Thus a signal is fed from memory module 62(FIG. 3) to sub-system controller 12 to indicate the charge status ofbattery 122. The present battery voltage monitoring circuit isconfigured to provide at least an 8 hour warning period prior to dataretention failure and typically provides a warning period several tensof hours longer than the worst case scenario.

A test voltage V_(TEST) may be applied to terminal 150c to allowin-circuit test equipment to be used to confirm the proper operation ofbattery voltage monitoring circuit 150. Voltage V_(REF) may thus be usedto ensure that comparator 151 and diode 154 are working properly.

Referring now to FIGS. 4 and 4A, a non-volatile single in-line memorymodule (NVSIMM) 160 includes a printed circuit board (PCB) 162 havingfirst and second opposing surfaces 162a (FIG. 4), 162b (FIG. 4A). PCB162 is preferably fabricated in compliance with industry-standardspecifications for a single in-line memory module (SIMM). PCB 162 isprovided having on one edge thereof an 80 pin edge-connector 164.Edge-connector 164 is here provided as a vertical edge connector. Thoseof ordinary skill in the art will recognize of course that non-verticaledge-connectors or any other type of connector may be employed. Thus,NVSIMM 160 is provided as a modular, removable, high density memoryarray which may be coupled to a supporting circuit board (motherboard)via connector 164. Furthermore, memory module 160 may be easilyinstalled or replaced by a different memory module having more memory,for example. Moreover, by providing memory module 160 as a SIMM, if asub-system controller fails, memory module 160 may be removed from thefailed sub-system controller and installed on a new operable sub-systemcontroller. Thus a user may rapidly resume system operation and avoidany loss of information or the need to perform a system reload.

Disposed on surface 162a is a rechargeable surface mount battery 165.Rechargeable battery 165 may be provided as a 90-100 mAh 3 V coin-cellof the type manufactured by Panasonic and identified as part numberVanadium Pentoxide Lithium VL3032-1F2. Alternatively, battery 165 may beprovided as the type manufactured by Sanyo and identified as part numberManganese dioxide Lithium ML2430-TT1.

Also disposed on surface 132a is an array of integrated circuit staticrandom access memory (SRAM) components 166a-166t generally denoted 166.Similarly, disposed on surface 162b is a second array of integratedcircuit SRAM components 168a-168t generally denoted 168. Each SRAM array166, 168 includes twenty 128K×8 bit 5 V SRAM IC's arranged as 524,288thirty-nine bit words (i.e. each array is 2 megabytes). The word widthis selected to accommodate a 32-bit data word and an accompanying 7-bitECC field. Each SRAM 166a-168t may be provided as the type manufacturedby Samsung and identified as part number KM681000ALT-7L, or as partnumber HM628128LT-7L manufactured by Hitachi or as part number UPD31000AGZ-7OLL manufactured by NEC or any other suitable device. TheNVSIMM 160 presently includes 2 Megabytes (MB) or 4MB of SRAM memoryhowever, any desired capacity may be employed within the limits ofcurrent memory IC capacities.

Thus, in this particular embodiment, NVSIMM 160 includes forty SRAMcomponents disposed on printed circuit board 162. It should be notedthat although forty SRAM components are disposed on printed circuitboard 162, the particular number of SRAM components which are disposedon PCB 162 is selected in accordance with a variety of factors includingbut not limited to the overall package size of PCB 162, the amount ofmemory provided by each SRAM array 166, 168 and the amount of memoryrequired in the system in which NVSIMM 160 is to be employed. Battery165 provides power to SRAM arrays 166, 168 during periods of power loss.

Coupled between battery 165 and SRAMs 166, 168 are a pair of batterymanagement circuits 170a, 170b generally denoted 170. Battery managementcircuits 170 monitor a supply voltage fed from a system voltage supplyto memory module 160 through connector 164. The battery managementcircuits 170 may be of the type manufactured by Dallas Semiconductor andidentified as part number DS1259S or the type manufactured by Maxim andidentified as part number MAX1259CWE. Other battery management circuitshaving equivalent electrical characteristics may also be used. In theevent the system voltage supply fails to provide the supply voltage tomemory module 160, battery management circuits 170a, 170b couple battery165 to SRAMs 166, 168. Thus, battery 165 provides power to SRAM arrays166, 168 and any information stored in SRAM arrays 166, 168 is therebypreserved.

The forty SRAM components 166, 168 are grouped into eight banks of fiveSRAMs each. That is, on side 162a of PCB 162, SRAMs 166a-166e provide afirst memory bank 172, SRAMs 166f-166j provide a second memory bank 174,SRAMs 166k-166o provide a third memory bank 176 and SRAMs 166p-166tprovide a fourth memory bank 178.

Likewise, on side 162b of PCB 162, SRAMs 168a-168e provide a firstmemory bank 180, SRAMs 168f-168j provide a second memory bank 182, SRAMs168k-168o provide a third memory bank 184 and SRAMs 168p-168t provide afourth memory bank 186.

Thus, the first four memory banks 172-178 are disposed on the first orso-called component side 162a of PCB 162 and the second four memorybanks 180-184 are disposed on the second or so-called circuit side 132bof PCB 162.

The battery voltage V_(NV).sbsb.--_(VCCA) provided at the output port130a (FIG. 3) of battery switch circuit 130 (FIG. 3) is coupled toone-half of the circuit components on the component side of PCB 162 andone-half of circuit components on the circuit side of PCB 162. Likewise,battery voltage signal V_(NV).sbsb.--_(VCCB) provided at output port130b (FIG. 3) of battery switch circuit 130 (FIG. 3) is coupled toone-half the circuit components on the component side 162a of PCB 162and one-half the circuit components on the circuit side 162b of PCB 162.

For example, battery voltage V_(NV).sbsb.--_(VCCA) may be coupled frombattery management circuit 170a to SRAMs 166a-166c in memory bank 172and also to SRAMs 166f-166h in memory bank 174. Battery voltageV_(NV).sbsb.--_(VCCB), on the other hand, would be coupled from batterymanagement circuit 170b to SRAMs 166d, 166e in memory bank 172 and alsoto SRAMs 166i and 166j in memory bank 174. Power is supplied to thememory banks 172-186 in this manner in part due to the electricalcharacteristics of battery management circuits 170. Specifically, thecurrent flow through battery management circuits 170 should preferablybe below a predetermined threshold current in order to ensure thatbattery management circuits 170 are working within specifications.

When one of the SRAMs 166, 168 are accessed, the amount of current drawnby the SRAM increases substantially. Conversely, when the SRAM is notaccessed (i.e. the SRAM is in a so-called standby mode) the currentdrawn by the SRAM is greatly reduced. Since only one of the memory banks172-186 may be accessed at any given time, it is desirable to minimizethe number of SRAM circuit components 166, 168 which are in activecurrent consumption mode and which are coupled to the same batterymanagement circuit 130a or 130b. Thus, in each SRAM memory bank 172-186,a portion of the SRAM components 166, 168 are powered via batterymanagement circuit 170a and the remainder of the SRAM components arepowered via battery management circuit 170b.

Thus, whenever a particular one of memory banks 170-186 is accessed, afirst one of the battery management circuits 170a should be coupled tothree SRAM components in active mode and seventeen SRAM components ininactive mode. Conversely, a second one of the battery managementcircuits 170b should be coupled to two SRAM components in active modeand eighteen SRAM components in inactive mode. Thus, five SRAMcomponents each in the same memory bank should be placed in their activemode and the remaining thirty five SRAM components should be placed intheir inactive mode. This results in each of the battery managementcircuits 170a, 170b having a worst case current which is within anacceptable current range of the battery management circuit. Those ofordinary skill in the art will recognize of course that a single batterymanagement circuit could be used if it could source sufficient currentfor the connected memory devices.

Also disposed on surface 162a are a plurality of data buffer circuits188a-188e generally denoted 188. Since address and data lines are fedthrough edge connector 164, address and data buffer circuits 188a-188eare disposed near the edge connector 164.

Data buffer circuits 188 may be provided as the type manufactured byTexas Instruments and identified as part number 74ABT245 or knowngenerically as 74245. Those of ordinary skill in the art will recognizeof course that any functionally equivalent part may be employed. In thisparticular embodiment a 40 bit bus is coupled between data buffers 188and SRAM arrays 166, 168. However as mentioned above only 39 bits areused for data and the error correction code.

An address multiplexer 190 may be provided, for example, as the typemanufactured by Texas Instruments and identified as part number74ABT162260 is disposed on surface 162a. Those of ordinary skill in theart will recognized of course that any part having equivalent functionaland electrical characteristics may also be used. Output signal lines ofmultiplexer 190 are coupled to an N bit address bus which is coupled toSRAM arrays 166, 168.

A battery voltage monitoring circuit 192 which may be similar to circuit150 described above in conjunction with FIG. 3A, is disposed oncomponent side 132a of PCB 132. The battery voltage monitoring circuit192 monitors the battery voltage and provides a battery status signal tothe sub-system controller via connector 164 to indicate the charge stateof battery 165.

A monitor circuit 194 is disposed on side 162b of PCB 162. Monitorcircuit 194 is coupled to the supply voltage provided to memory module160 from the system voltage supply and operates in a manner similar tomonitor circuit 110 described above in conjunction with FIG. 3. Monitorcircuit 194 may be provided as the type manufactured by DallasSemiconductor and identified as part number DS1233. Those of ordinaryskill in the art will recognize of course that any circuit capable ofdetecting a change in the voltage level of a supply voltage andproviding an output signal in response thereto may also be used.

In an alternative embodiment employing NiCd cells, and referring to FIG.5A-5B, a battery circuit 200 includes a battery 202 which includes aplurality of voltage cells 203a-203c each of which corresponds to anickel cadmium (NiCd) 1.2 volt (V) cell. Those of ordinary skill in theart will recognize of course that the particular type of cell, thenumber of cells and the voltage level of each cell may be selected tosatisfy particular application requirements including but not limited tothe overall voltage which must be supplied by battery 202 as well as theform factor of the battery 202.

Battery 202 provides a voltage V_(BATT) at an output terminal 202a.Output battery terminal 202a is coupled to a charge circuit 204 at firstand second terminals 204a, 204b and 204c. Charge circuit 204 includes acharge control circuit 208 which may be provided as an integratedcircuit. For example, charge control circuit 208 may be provided as thetype manufactured by Integrated Circuit Systems, Inc. and identified aspart number ICS 1700.

In brief overview, the charge control circuit 208 initiates batterycharge and discharge cycles by providing a periodic series of logiclevel output signals, some of which initiate a battery charge cycle andsome of which initiate a battery discharge cycle. The charge anddischarge signals are separated by rest periods during which time thebattery 202 is neither being charged nor discharged, but monitored forits cell voltage.

The periodic charge and discharge cycles are provided to optimize thecharge and performance of the NiCd battery. That is, the NiCd battery202 should be charged for period of time, allowed to rest for a periodof time and then discharged for a relatively small period of time. Thissequence is repeated by the charge control circuit 208. Thus, suffice itto say that the charge control circuit 208 controls the operation of thecharging circuit 204.

The charge control circuit 208 has two operating modes. A first or highcharge operating mode is used when the charge control circuit 208 ischarging the battery 202 at a high rate. Thus in the first operatingmode, the time period in between the charge and discharge cycles isrelatively small. In the high charge mode, when the battery 202 isdepleted, the battery 202 can be fully charged in thirty minutes.

A second operating mode of the charge control circuit 208 is generallyreferred to as a maintenance mode. In the maintenance mode, the timeperiod between the charge and discharge signals is longer than in thehigh charge mode. Thus, the charge control circuit 208 continuouslycharges the battery 202, however, once the battery 202 is determined tobe fully charged the charge control circuit 208 will enter themaintenance mode in which the charge control circuit 208 alters thecharge and discharge cycles.

The charge control circuit 208 stops charging the battery 202 if any oneof several conditions occur. For example, the charge control circuit 208stops charging the battery 202 or automatically switches into themaintenance mode if (a) the charge control circuit 208 determines thatthe battery 202 is fully charged; or (b) the charge control circuit 208stops charging the battery 202 if the battery temperature falls outsideof a predetermined temperature range determined by a temperature monitorcircuit 224. In addition to the above, the charge control circuit 208stops charging the battery 202 if the charge control circuit 208 isplaced in a reset mode or if the voltage level V_(CC) falls below apredetermined threshold.

In the present embodiment, the charge control circuit 208 stops chargingthe battery 202 by providing the logic level output signals having avoltage level corresponding to a logic level 0. For example, when thetemperature about battery 202 is outside the predetermined temperaturerange the charge control circuit output signals which are TTL logicsignals are placed at logic level 0.

In addition to the charge control circuit 208, the charge circuit 204also includes a charging transistor 214 having a first terminal 214acoupled to a node 213, a second terminal 214b coupled to a firstterminal of a resistor R1 and a third terminal coupled through aresistor R214 to an output port 216d of a switch control circuit 216. Asecond terminal of the resistor R1 is coupled to the battery terminal202a and to a first terminal of a resistor R2. A second terminal of theresistor R2 is coupled to a zener diode D1 as shown. The resistor R2 andthe zener diode D1 are appropriately selected having values such that inthe event that the voltage V_(CC) rises above a predetermined voltagelevel the zener diode D1 will conduct and thus protect the battery 202from being exposed to an excessive voltage.

When charge circuit 204 is in a charge mode, transistor 214 couples avoltage at node 213 to the first terminal of the resistor R1 and thebattery 202 is charged by a current provided through the resistor R1.Thus, the resistance value of the resistor R1 is selected such that inthe charge mode a predetermined current flows to the battery 202.

It should be noted that although the charge control circuit 208 controlsthe charge and discharge cycles, the charge level in terms of current isdetermined by the user. In this particular embodiment, the resistancevalue of a resistor R1 determines the charge current level inconjunction with the battery voltage. If the resistor R1 is providedhaving a relatively small resistance value then a high current flowsinto the battery 202. However, if the resistor R1 is provided having arelatively large resistance value, then a relatively low current isprovided to the battery 202.

Charge circuit 204 further includes a discharge signal path provided bya discharge transistor 222 having a first terminal 222a coupled tobattery terminal 202a, a second terminal 222b coupled to a firstterminal of a termination 223 and a third terminal 222C coupled througha resistor R222 to an output port 216e of the switch control circuit216. The termination 223 includes a plurality of resistors 223a-223ehaving resistance values selected to discharge a predetermined amount ofcurrent based upon the operating mode of the charge control circuit 208.

When charge circuit 204 is in a discharge mode, the transistor 222provides a discharge signal path between battery terminal 202a andground through the resistor network 223. The discharge signal path isneeded since, as mentioned above, the charge control circuit 208 employsan algorithm having a charge and a discharge cycle and thus chargecontrol circuit 208 periodically discharges the battery 202 for a shortamount of time.

As mentioned above, the NiCd cells 203a-203c are charged continuously bythe charging circuit 204 and can be fully recharged from a dischargecondition in 30 minutes. It will be appreciated of course that thecharging time is dependent upon the resistance value of resistor R1. Insome applications it may be desirable to provide resistor R1 having avalue which results in a battery recharge time of as along as 24 hours.

When battery circuit 200 operates in a battery back-up mode a transistor205 couples the battery voltage V_(BATT) to a volatile memory array (notshown). The battery 202 provides the voltage to the memory array for apre-determined period during which the memory array can retain theinformation stored therein. The predetermined period of time dependsupon a variety of factors including but not limited to the size of thememory array. For example, in the present embodiment the battery voltageis sufficient to provide a minimum of 30 days of data retention for 2megabytes (MB) of pseudo static RAM (PSRAM). That is, when the volatilememory array is provided as PSRAM, the standby power requirement of thePSRAM are such that battery 202 can power the PSRAMs for approximately30 days. A larger battery may of course also be used in which case, thePSRAM memory array could maintain data for more than thirty days.

The length of data retention time will depend upon a variety of factorsincluding but not limited to memory size and type, battery size and typeand temperature. In some applications it may be desirable to provide aminimum of 15 days of data retention for 4 MB of PSRAM or alternatively,it may be desirable to provide one week of data retention for 8 MB ofPSRAM.

A pair of resistors R100 and R102 are coupled input terminals 208a, 208bof the charge control circuit 208. The resistance values of resistorsR100 and R102 notify the charge control circuit 208 the rate at whichthe charge control circuit 208 will operate to charge the battery 202.In the present embodiment, the resistors R100, R102 are provided havingresistance values which indicate that the charge control circuit 208 isin the high charge mode. This mode is related to the time of chargingand is unrelated to the maintenance charge or the hard charge operationsdescribed above. Thus the resistors R100, R102, notify the chargecontrol circuit 208 the rate at which the battery 202 is being charged.There are four different charging rates available as mentioned above andin the present embodiment, the battery 202 is being charged at the highcharge rate such that the battery 202 can be rapidly re-charged. Thoseof ordinary skill in the art will recognize of course that in someapplications other charge rates may be preferred.

A capacitor C2 and a diode D2 are coupled as shown to provide a resetcircuit which is coupled to a reset port 208c of the charge controlcircuit 208. The charge control circuit 208 receives the voltage V_(CC)through the reset circuit.

Charge control circuit 208 receives on an input port 208d a temperaturesense input signal from a temperature circuit 224. The charge controlcircuit 208 monitors the temperature sense signal fed thereto on port208d via the temperature monitor circuit 224 in accordance with thepredetermined algorithm of charge control circuit 208.

The charge control circuit 208 includes an internal oscillator used togenerate an internal clock signal. An input terminal 208e of the chargecontrol circuit 208 is coupled through a resistor R104 and a capacitorC4 as shown to the node 213 such that card voltage V_(CC) is provided tothe internal oscillator circuit of charge control circuit 208 togenerate the internal clock signal. After charge control circuit 208receives a reset signal on terminal 208c the charge control circuit 208uses the internal oscillator to count some predetermined period of timeprior to implementing the algorithm.

Charge control circuit 208 at input port 208f monitors the batteryvoltage V_(BATT) through a voltage divider circuit which here includes apair of voltage divider resistors R3, R4 and a noise suppressioncapacitor C3 coupled as shown. The charging circuit 204 is coupled tothe battery terminal 202a through the voltage divider circuit such thatcharge control circuit 208 can monitor the battery voltage V_(BATT). Thevoltage divider circuit is required because the charge control circuit208 is intended to examine the voltage from a single battery cell and inthe present embodiment, battery 202 includes three cells 203a--203c. Thebattery voltage V_(BATT) is monitored at predetermined times inaccordance with the battery charging algorithm.

Thus, the charge control circuit 208 monitors a temperature sense inputsignal at terminal 208d, a card voltage at terminal 208c and a batteryvoltage at terminal 208f.

The charge control circuit 208 provides on output ports 208g, 208h thelogic level output signals V_(CHARGE) and V_(DISCHARGE) in accordancewith the predetermined algorithm. The charge control circuit outputports 208g, 208h are coupled to input ports 216g, 216h respectively ofthe switch control circuit 216. Thus the charge control circuit 208provides the logic level output signals V_(CHARGE) and V_(DISCHARGE) tothe switch control circuit 216.

The charge control circuit 208 provides a first status signal V_(ERROR)on an output port 208i and a second status signal V_(MODE) on an outputport 208j. The status signals V_(ERROR) and V_(MODE) are coupled to LEDs236, 236' to provide visual indicators of the status of the circuit 204.

In the present embodiment, switch control circuit 216 is a charge pumpand level translation circuit which may, for example, be of the typemanufactured by Maxim Corporation and identified as part number Max 620or Max 621. Those of ordinary skill in the art will recognize of coursethat any switch control circuit having suitable electricalcharacteristics may also be used. Switch control circuit 216 receivescharge control signals V_(CHARGE), V_(DISCHARGE) from the charge controlcircuit 208 and also receives on input port 216f a control signalV_(RESET) from a voltage detect circuit 206.

As mentioned above charge control signals V_(CHARGE) and V_(DISCHARGE)are logic level signals. When signal V_(CHARGE) is provided as a logichigh signal (i.e. a logic level 1) the switch control circuit 216provides a signal to control terminal 214c of charging transistor 214 tothus bias transistor 214 into its conductive state. In its conductivestate, transistor 214 provides a low impedance signal path between thecard voltage V_(CC) at node 213 and resistor R1 and thus a current flowsto battery 202 thus charging the battery 202.

As also mentioned above, the battery 202 is coupled to the memory array(not shown) through the transistor 205. The battery terminal 202a isalso coupled to a first terminal 205a of the transistor 205. A secondterminal 205b of transistor 205 is coupled to the volatile random accessmemory array (not shown) which may be provided for example as apseudo-static random access memory array (PSRAM). A control terminal205c of transistor 205 is coupled to a terminal 206b of the detectioncircuit 206 which may be for example part number LTC 690 as the typemanufactured by Linear Technology, Inc. Other detection circuits havingequivalent electrical and functional characteristics may of course alsobe used.

When transistor 205 is biased into its conductive state, the transistor205 provides a signal path through which the battery voltage V_(BATT) iscoupled to the non-volatile RAM to thus provide the battery voltageV_(BATT) to the non-volatile RAM in the event that the system voltageV_(SIMM).sbsb.--_(VCC) fails or is otherwise unavailable to thenon-volatile RAM. Thus in the event of a system voltage failure, thebattery voltage V_(BATT) is coupled to the PSRAM through the transistor205.

To prevent a significant voltage drop from occurring when transistor 205is turned off and transistors 210, 212 are turned on to thus decouplethe memory array from the battery voltage and couple the memory array tothe system voltage, a capacitor C1 is coupled as shown to store chargeand thus maintain the predetermined voltage level for the brief periodof time it takes for transistors 210 and 212 to turn on. It isundesirable for the voltage provided to the memory to drop below apredetermined voltage level when switching between the battery voltageV_(BATT) and system voltage V_(SIMM).sbsb.--_(VCC) and vice-versa. Thuscapacitor C1 maintains the voltage while switch 205 is turning off andswitches 210 and 212 are turning on and prevents any significant voltagedrop from occurring when a change is being made between battery voltageV_(BATT) and system voltage V_(SIMM).sbsb.--_(VCC).

It should be noted that the transistor 205 is provided as a logic levelP-channel field effect transistor (PFET) while transistors 210, 212 and214 are provided as N-channel logic level FETs (NFETs) and in particularN-channel MOSFETs. This selection was made since PFETs conduct when thevoltage applied to the gate terminal thereof is lower than the inputvoltage whereas NFETs, on the other hand, conduct when the voltageapplied to the gate terminal is greater than the input voltage. Thus,when the card 200 is powered down (i.e. when V_(SIMM).sbsb.--_(VCC) isoff) V_(RESET) is low and the FET 205 will conduct since the drain is ata higher potential than the gate. Those of ordinary skill in the artwill recognized of course that other types of FETs and correspondingswitching schemes may also be employed.

Transistor 205 is biased into its conductive state in the followingmanner. An input terminal 206a of detection circuit 206 is coupled tothe system voltage V_(SIMM).sbsb.--_(VCC). Voltage detection circuit 206includes an internal comparator which measures the voltage level of thesystem voltage V_(SIMM).sbsb.--_(VCC). Circuit 206 determines whether ornot system voltage V_(SIMM).sbsb.--_(VCC) has reached a predeterminedthreshold and thus whether the card voltage V_(CC) can be provided tothe remaining circuit components on the battery circuit 200.

When detection circuit 206 senses that system voltageV_(SIMM).sbsb.--_(VCC) is below a predetermined threshold voltage,detection circuit 206 provides a signal V_(RESET) to control terminal205c of the transistor 205. In response to the V_(RESET) signal,transistor 205 provides a low impedance signal path between the batteryterminal 202a and the volatile RAM.

The system voltage V_(SIMM).sbsb.--_(VCC) is also directly coupled to apair of transistors 210, 212 at terminals 210a, 212a respectively.Transistors 210, 212 are here each provided as MOSFET transistors.Transistor 210 has a second terminal 210b coupled to the PSRAM memoryarray and a third terminal 210c coupled to terminal 216b of the switchcontrol circuit 216 through a resistor R210. When battery circuit 200operates in a normal mode the system voltage V_(SIMM).sbsb.--_(VCC) iscoupled to the memory array through transistor 210.

Transistor 212 has a second terminal 212b coupled to the node 213 and athird terminal 212c coupled through a resistor R212 to the switchcontrol circuit 216 at terminal 216c. The transistor 212 acts as aswitch to provide the card voltage V_(CC) to particular circuitry of thebattery circuit 200.

It should be noted that transistor 205 is biased by the battery 202rather than by the system voltage V_(SIMM).sbsb.--_(VCC) or the cardvoltage V_(CC). This is because it is necessary to power the memoryarray from the battery 202 when no system or card voltage is present.Thus transistor 205 must remain operational when the system voltageV_(SIMM).sbsb.--_(VCC) is unavailable.

Transistors 210 and 212 on the other hand are coupled to and biased bythe system voltage V_(SIMM).sbsb.--_(VCC) and transistor 214 is biasedby the card voltage V_(CC). It is neither necessary nor desirable topower the transistors 210, 212 or the remaining circuitry of the batterycircuit 200 from the battery 202 since this would undesirably drain thebattery 202 when the system voltage V_(SIMM).sbsb.--_(VCC) isunavailable.

System voltage V_(SIMM).sbsb.--_(VCC) is also coupled to a power pin216a of the switch control circuit 216. Thus, switch control circuit 216directly receives the system voltage V_(SIMM).sbsb.--_(VCC). Capacitors218, 219 and 220 are coupled to the switch control circuit 216 as shownand used by the charge pump of switch control circuit 216 to increasethe voltage at output ports 216b-216e to a predetermined voltage havinga value approximately eleven and one-half volts above the system voltageV_(SIMM).sbsb.--_(VCC).

Thus, system voltage V_(SIMM).sbsb.--_(VCC) is directly coupled tovoltage detect circuit 206, transistors 210, 212 and to switch controlcircuit 216.

As mentioned above, detection circuit 206 detects whether voltageV_(SIMM).sbsb.--_(VCC) is falling below a predetermined threshold. Ifvoltage V_(SIMM).sbsb.--_(VCC) falls below a predetermined thresholdvoltage, detection circuit 206 provides the signal V_(RESET) at outputport 206a and signal V_(RESET) is coupled to input port 216f of switchcontrol circuit 216. In response to the signal V_(RESET), switch controlcircuit 216 provides bias signals on terminals 216b, 216c which bias thetransistors 210, 212 into their non-conductive states. In itsnon-conductive state transistor 210 decouples the non-volatile RAM fromthe system voltage V_(SIMM).sbsb.--_(VCC). Similarly in itsnon-conductive state, transistor 212 prevents the card voltage V_(CC)from being provided to the circuit components of the circuit 200.

When switch control circuit 216 receives the signal V_(CHARGE) on inputport 216g switch circuit 216 biases transistor 214 into its conductivestate and thus, transistor 214 couples the voltage V_(CC) at node 213through the resistor R1 to battery terminal 202a.

The battery charge transistor 214 is turned on and off via the switchcontrol circuit 216 to selectively supply the card voltage V_(CC) to thebattery 202 to thus charge the battery 202 in accordance with thecharging algorithm executed by the charge control circuit 208. When thetransistor 214 is biased into its conductive state, the charge signal isprovided through the resistor R1 to the battery 202.

When switch control circuit 216 receives a signal V_(DISCHARGE) on inputport 216h, switch control circuit 216 biases the transistor 222 into itsconductive state. In its conductive state, transistor 222 provides thedischarge signal path between battery terminal 202a and ground throughthe termination network 223.

Battery circuit 200 further includes the temperature monitor circuit 224coupled to the charging circuit 204 at terminal 204d. The temperaturemonitor circuit 224 provides an output signal which indicates whetherthe monitored temperature is outside of the prescribed temperaturelimits. Temperature monitor circuit 224 provides at output port 224c, anoutput signal indicative of whether the battery temperature is within apredefined range. Temperature monitor circuit 224 includes a temperaturesensor 226 which provides at an output port 226a an output signal havinga voltage amplitude proportional to the ambient temperature attemperature sensor 226. In some embodiments it may be preferable toplace sensor 226 in direct contact with battery 202.

Output port (op amp) 226a is coupled to a first input port of a firstoperational amplifier 228 which may for example, be provided as an LM358A. A second input port of op amp 228 is coupled to a first outputport of a voltage reference circuit 230. Voltage reference circuit 230provides a reference voltage V_(HI) to the second input port of op amp228.

As the ambient temperature in the vicinity of temperature sensor 226rises, temperature sensor 226 provides at output port 226a a signalV_(TEMP) having a voltage amplitude proportional to the ambienttemperature at temperature sensor 226. When the temperature rises to apredetermined level such that the voltage V_(TEMP) is greater than thereference voltage V_(HI) op amp 228 provides a control signal to atemperature monitor port 204d of charging circuit 204 which is coupledto charge control terminal 208d. In response to the control signal fromcomparator 228 charging circuit 204 ceases to charge battery 202.

Temperature sensor output port 226a is also coupled to a first inputport of a operational amplifier 232 which also may be provided as an LM358A. A second input port of op amp 232 is coupled to a second outputport of voltage reference circuit 230. Voltage reference circuit 230provides a reference voltage V_(LO) to the second input port of op amp232. As the ambient temperature in the vicinity of temperature sensor226 decreases, temperature sensor 226 provides at output port 226a thesignal V_(TEMP). When the temperature decreases to a predetermined levelsuch that the voltage V_(TEMP) is lower than the reference voltageV_(LO), comparator 232 provides a control signal to temperature monitorport 204d of charging circuit 204 which is coupled to charge controlterminal 208d. In response to the control signal from op amp 232charging circuit 204 ceases to charge the battery 202.

Thus, temperature monitor circuit 224 prevents the charging circuit 204from charging battery 202 when the ambient temperature in the vicinityof temperature sensor 226 is above or below the predeterminedthresholds. Thus, it is desirable to place temperature sensor 226 inphysical proximity to the battery 202.

The charge control circuit 208 thus monitors the signal provided fromtemperature monitor circuit 224 and in response to a signal fed theretofrom the temperature circuit 224, places the V_(CHARGE) andV_(DISCHARGE) at logic level zero which thereby causes switch controlcircuit 216 to turn off transistors 214 and 222.

If charging circuit 204 senses an error while in a charging mode, chargecontrol circuit 208 provides a signal V_(ERROR) to an indicator circuit234 which includes a light emitting diode 236 and a pair of resistors238, 240 coupled as shown. Error signal V_(ERROR) is also provided to aninput port of a status indicator circuit 242.

Indicator circuit 234 also includes an LED 236' and a pair of resistors238', 240'. LED 236' receives a signal V_(MODE) from charge controlcircuit 208. In response to the V_(MODE) signal LED 236' blinks toindicate that charging circuit 204 is providing a charge current to thebattery 202. The V_(MODE) signal may, for example, cause LED 236' toblink at a particular rate to indicate the operating mode of the chargecontrol circuit 208. If the charge control circuit 208 operates in itsmaintenance mode, then LED 236' may blink at a rate of once per second.Thus signal V_(MODE) indicates whether charge control circuit 208 isoperating in one of its normal charge modes or in its maintenance mode.Thus, LEDs 236, 236' provide a visual indication of whether or not aproblem exists with the battery based on the voltage input or if thetemperature goes outside a predetermined temperature range.

Status circuit 242 includes a plurality of resistors 244-252 each havinga first terminal coupled to system supply voltage V_(CC) and a secondterminal coupled to an input port of a buffer circuit 254. The secondterminals of resistors 244 and 246 are coupled to ground through seriesresistors 250 and 252 respectively. The resistance values of each ofresistors 244-252 is selected such that signals ID₀, ID₁, and ID₂provided on output ports 254d-254f of buffer circuit 254 have valueswhich indicate the amount of non-volatile RAM coupled to battery circuit200.

For example, if the memory array includes 2 MB of non-volatile RAM,signals ID₀ -ID₂ take on a first set of values. If the memory arrayincludes 4 MB of RAM signals ID0-ID2 take on a second different set ofvalues. Similarly, signals ID0-ID2 take on a third distinct set ofvalues to indicate an error in battery circuit 200 or in the memoryarray. Thus, battery circuit 200 provides a three bit identificationcode to sub-system controller 12 (FIG. 1). The code identifies memorymodule characteristics including but not limited to the module capacityand an error status.

Battery Circuit Operation

The battery circuit 200 operates in the following manner. Assume at atime T=0 power is applied to the battery charge circuit 200. Voltagedetection circuit 206, switch control circuit 216 and transistors 212,214 are directly coupled to the system voltage V_(SIMM).sbsb.--_(VCC).Thus upon initial power up, circuits 206 and 216 receive system voltageV_(SIMM).sbsb.--_(VCC) and become operable, however, the remainingactive circuit components on the card 200 have not yet received power.Battery 202 provides the battery voltage V_(BATT) at terminal 202a.

Upon initial power up, the transistor 214 is in its unbiased state andthus prevents the voltage V_(BATT) from reaching the node 213.Transistor 205 is in its conductive state to thus couple the batteryvoltage V_(BATT) to the PSRAMs.

Detection circuit 206 determines whether or not the system voltageV_(SIMM).sbsb.--_(VCC) is at the proper level to power up the memoryarray and those circuit components of battery circuit 200 which do notyet have a voltage signal provided thereto. If the system voltageV_(SIMM).sbsb.--_(VCC) fails to reach the predetermined thresholdvoltage then voltage detection circuit 206 prevents the system voltageV_(SIMM).sbsb.--_(VCC) from being coupled to the memory array or to anyother circuit components of battery circuit 200 by continuing to assertthe V_(RESET) signal. If the system voltage V_(SIMM).sbsb.--_(VCC)reaches the predetermined voltage level, detection circuit 206de-asserts the reset signal V_(RESET) to input terminal 216f of theswitch control circuit 216 and to the gate electrode 205c of transistor205. Transistor 205 thus decouples the battery 202 from the memoryarray.

When switch control circuit 216 receives the de-asserted V_(RESET)signal, switching control circuit 216 provides a bias signal to the gateterminals of transistor 210 to bias the transistor 210 into itsconductive state. When biased into its conductive state, transistor 210couples the system voltage V_(SIMM).sbsb.--_(VCC) to the PSRAMs coupledto transistor terminal 210b.

Similarly, in response to the de-asserted V_(RESET) signal, switchcontrol circuit 216 also provides a bias voltage to the gate terminal oftransistor 212 and biases the transistor 212 into its conductive state.In its conductive state transistor 212 couples the system voltageV_(SIMM).sbsb.--_(VCC) to node 213 to thus provide the card voltageV_(CC) at the node 213. Thus, transistor 212 allows the card voltageV_(CC) to be provided to the remaining active circuit components on thebattery circuit 200. For example, the card voltage V_(CC) is provided tothe temperature monitoring circuit 224 at terminals 224a, 224b; to thebuffer circuit 242; and to the charging circuit 204 at terminals 204e,204f.

Thus when system voltage V_(SIMM).sbsb.--_(VCC) is first supplied to thebattery circuit 200, the voltage V_(SIMM).sbsb.--_(VCC) rises to apredetermined threshold voltage which may be 5 volts, for example.Circuit components 206 and 216 and transistors 210, 212 each have thesystem voltage V_(SIMM).sbsb.--_(VCC) provided thereto while theremainder of the circuit components on the battery circuit 200 do notreceive any voltage.

Based on the voltage level of the system voltage V_(SIMM).sbsb.--_(VCC)provided to the voltage detection circuit 206, the remaining circuitcomponents of the battery circuit 200 will either receive a voltage ornot. If the system voltage V_(SIMM).sbsb.--_(VCC) provided to thebattery circuit 200 does not reach the proper level for at least apredetermined period time, the battery 202 will remain coupled to thememory array through the transistor 205 and the remaining circuitcomponents of the battery circuit 200 will not have a voltage appliedthereto.

Assuming the voltage V_(SIMM).sbsb.--_(VCC) rises to the predeterminedvoltage level, the card voltage V_(CC) is provided to the remainingcircuit components of the battery circuit 200, the voltageV_(RAM).sbsb.--_(VCC) is coupled to the memory array through thetransistor 210 and the battery 202 is de-coupled from the memory array.

The charge reset input terminal 208c of the charge control circuit 208monitors the voltage V_(CC) as modified by the reset circuit formed bycapacitor C2 and diode D2. Thus, as system voltage is provided to thebattery circuit 200, voltage is provided to the charge control circuit208 based on a time constant of the reset circuit.

Upon initial application of the system voltage V_(SIMM).sbsb.--_(VCC),the voltage V_(SIMM).sbsb.--_(VCC) has a rising voltage characteristicwhich reaches a predetermined level at time T₁. Since the card voltageV_(CC) is switched through the transistor 212 the card voltage V_(CC)rises to a predetermined voltage level with a characteristic similar toa step function characteristic at a time T₂ =T₁ +t₁

Capacitor C2 is selected having a relatively large capacitance valuewhich may typically be about one microfarad, for example, and thus thereis some period of time T₃ =T₂ +t₂ when the signal on the charge resetterminal 208c of the charge control circuit 208 is at a logic low andthe voltage V_(CC) is at a logic high. In this condition, the chargecontrol circuit 208 is in a reset mode. Thus upon initial power up ofthe battery circuit 200 the charge control circuit 208 initially entersa reset mode.

The diode D2 is provided as part of the reset circuit such that when thevoltage V_(CC) is removed, the capacitor C2 rapidly discharges throughthe diode D2. Thus, the charge control circuit 208 reset time is basedon the capacitance value of the capacitor C2.

The charge control circuit 208 next examines the level of the batteryvoltage V_(BATT). At this time transistor 205 is turned off becauseV_(RESET) is a logic high signal and, in the present embodiment,transistor 205 is provided as a PFET. Transistors 210 and 212 are on,transistor 214 is off and transistor 222 is off. Thus, the chargecontrol circuit 208 examines the battery voltage V_(BATT) through thevoltage divider resistors R3, R4 and based on the voltage level of thebattery voltage the charge control circuit 208 determines whether or notto enter a charge mode.

Thus the charge control circuit 208 monitors the battery voltage and,via the internal clock of the charge control circuit 208, at apredetermined period of time, the charge control circuit 208 charges anddischarges the battery 202 as described herein above.

Having described preferred embodiments of the invention, it will beapparent to those of ordinary skill in the art that other embodimentsincorporating the inventive concepts may be employed. Accordingly, theseembodiments should be viewed as exemplary and the invention should belimited only by the scope and spirit of the appended claims.

What is claimed is:
 1. A non-volatile memory module for use in a systemhaving a predetermined system voltage comprising:a mounting substratehaving an input port and an output port; a memory array including atleast one volatile memory mounted on the mounting substrate, saidvolatile memory having a power input terminal for coupling power to saidvolatile memory in normal operation; a rechargeable battery mounted onthe mounting substrate, said rechargeable battery having first andsecond connections; a switch circuit mounted on said mounting substrateand having an input terminal coupled to said rechargeable battery, anoutput terminal coupled to the power input terminal and a controlterminal operative to cause said switch to assume one of a highimpedance and a low impedance state in response to a control signal; acharging circuit mounted on the mounting substrate, said chargingcircuit having a charging circuit output coupled to said first batteryconnection and a charging circuit input for coupling to saidpredetermined system voltage; a system voltage monitoring circuit havinga first port coupled to said input port of the mounting substrate andhaving an output port coupled to the control terminal of said switchcircuit, wherein said system voltage monitoring circuit activates thecontrol terminal of said switch in response to the predetermined systemvoltage reaching a predetermined threshold voltage; a battery voltagemonitor circuit disposed on said mounting substrate, said batteryvoltage monitor circuit having an input port coupled to said firstbattery connection and having an output port coupled to said output portof said mounting substrate, said battery voltage monitor circuit beingoperative to provide a warning signal at said output port when thevoltage at said first battery connection drops below a predeterminedvalue, wherein said rechargeable battery includes one of a lithium celland a nickel cadmium cell and said memory array includes one of adynamic random access memory array and a pseudo-static random accessmemory array; and a battery temperature monitor circuit disposed on saidmemory module and coupled to said charging circuit, said batterytemperature monitor circuit being operative to produce an output voltageindicative of the ambient temperature, said battery temperaturemonitoring circuit having a voltage threshold and being operative topermit charging of said rechargeable battery only if the batterytemperature monitoring circuit output voltage is below said voltagethreshold.
 2. A single in-line memory module (SIMM) for use in a systemhaving a predetermined system voltage and adapted for use on amotherboard having a SIMM connector disposed thereon wherein themotherboard provides said predetermined system voltage to the memorymodule, said memory module comprising:a printed circuit board; avolatile memory array disposed on said printed circuit board; aplurality of conductive pads arranged on the edge of said printedcircuit board in a pattern adapted to interface with the SIMM connectoron the motherboard; a battery disposed on said printed circuit board; acharging circuit disposed on said printed circuit board and coupled tosaid battery, said charging circuit being coupleable to saidpredetermined system voltage through at least one of said conductivepads; and a switch circuit having a control terminal, disposed on saidprinted circuit board and coupled between said battery and said volatilememory array and operative to electrically connect said battery to saidvolatile memory array and to disconnect said predetermined systemvoltage from said volatile memory array in a first state and toelectrically disconnect said battery from said volatile memory array andto couple said predetermined system voltage to said volatile memoryarray in a second state; and a power monitoring circuit having a firstport coupled to a first one of the plurality of conductive pads, andhaving a second port coupled to the control terminal of said switchcircuit wherein said power monitoring circuit detects changes in thesystem voltage level and in response to the changes in the systemvoltage level said power monitoring circuit provides a control signal tothe control terminal of said switch circuit to place said switch circuitin one of the first state and the second state.
 3. The single in-linememory module of claim 2 further comprising a battery voltage monitorcircuit disposed on said printed circuit board, having an input portcoupled to an output port of said battery and having an output portcoupled to a second one of said plurality of conductive pads.
 4. Thenon-volatile in-line memory module of claim 3 wherein said batteryincludes one of a lithium cell and a nickel cadmium cell.
 5. Thenon-volatile in-line memory module of claim 4 wherein said memory arrayincludes one of a dynamic random access memory array and a pseudo-staticrandom access memory array.
 6. The single in-line memory module of claim5 further comprising a temperature monitor circuit disposed on saidprinted circuit board and coupled to said charging circuit.
 7. A diskstorage sub-system coupled between a host processor and a plurality ofdisk drives, the disk storage sub-system comprising:a sub-systemcontroller; a logic controller coupled to said sub-system controller,said logic controller for receiving and providing data and addressinformation between said sub-system controller and the plurality of diskdrives; a host interface circuit having a first input port coupled tosaid sub-system controller, having a second input port adapted to coupleto the host processor and having a control logic port coupled to saidlogic controller; a disk drive interface circuit having a first inputport coupled to said sub-system controller, having a second port adaptedto coupled to each of the plurality of disk drives and having a controllogic port coupled to said logic controller; and a non-volatile singlein-line memory module (SIMM), coupled to said logic controller, saidnon-volatile SIMM including:a volatile memory array; a battery; and aswitch circuit having a first terminal coupled to said volatile memoryarray, having a second terminal coupled to said battery and having acontrol terminal coupled to a control port of said memory circuit. 8.The disk storage sub-system of claim 7 wherein said non-volatile SIMMfurther comprises a system voltage monitoring circuit disposed on saidnon-volatile SIMM, having a first port coupled to an input port of thememory circuit and having an output port coupled to the control terminalof said switch circuit.
 9. The disk storage sub-system of claim 8wherein said nonvolatile SIMM further comprises a battery chargingcircuit coupled to said battery.
 10. The disk storage sub-system ofclaim 9 wherein said non-volatile SIMM further comprises a temperaturemonitor circuit coupled to said battery charging unit.
 11. The diskstorage sub-system of claim 9 wherein said battery includes at least afirst one of a lithium cell and a nickel cadmium cell.
 12. A diskstorage system for storing data from a host computer, said disk storagesystem comprising:a disk drive; a disk controller having a firstinterface coupled to the host computer, said disk controller forreceiving data to be written to said disk drive, said disk controllerincluding:a write cache for temporarily storing the data to be writtento said at least one disk drive; said disk controller providing a signalto the host to indicate that the data has been stored prior to theactual storage of the data on said disk drive; said write cacheincluding a non-volatile single in-line memory module comprising:amemory array including a volatile memory mounted on the memory module,said volatile memory having a power input terminal; a rechargeablebattery mounted on the memory module; and a switch circuit having afirst terminal coupled to said rechargeable battery, a second terminalcoupled to said the power input terminal of said volatile memory, saidswitch circuit having a control terminal operative to cause said switchto assume one of a high impedance and a low impedance state in responseto an applied signal.
 13. The disk storage system of claim 12 whereinsaid volatile memory is a first one of a plurality of volatile memorieswith the second terminal of said switch circuit coupled to the powerinput terminal of each of said plurality of volatile memories.
 14. Thedisk storage system of claim 13 wherein said disk drive is a first oneof a plurality of disk drives wherein said plurality of disk drives arecoupled to provide a redundant array of inexpensive disks.
 15. The diskstorage system of claim 14 wherein said non-volatile memory modulefurther comprises a charging circuit coupled to said battery.
 16. Thedisk storage system of claim 15 wherein said non-volatile memory modulefurther comprises a system voltage monitoring circuit having a firstport coupled to the input port of the memory module and having an outputport coupled to the control terminal of said switch circuit.
 17. Thedisk storage system of claim 16 wherein said non-volatile memory modulefurther comprises a battery voltage monitor circuit having an input portcoupled to an output port of said battery and having an output portcoupled to an output port of said non-volatile memory module.
 18. Thedisk storage system of claim 17 wherein said non-volatile memory moduleincludes a first one of a static random access memory and apseudo-static random access memory.
 19. The disk storage system of claim18 wherein said non-volatile memory module further comprises atemperature monitor circuit coupled to said charging circuit.